1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device including a bit line pre-sense amplifier and a bit line main sense amplifier.
2. Description of the Related Art
In general, a semiconductor memory device, such as double data rate synchronous DRAM (DDR SDRAM), performs a read operation and a write operation in response to several external signals. The write operation means an operation for storing data in a memory cell corresponding to an address, and the read operation means an operation for outputting data stored in a memory cell, corresponding to an address. The semiconductor memory device may include a variety of circuits for performing the read operation and the write operation.
FIG. 1 is a circuit diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a memory cell 110, a bit line pre-sense amplifier 120, a bit line main sense amplifier 130, and a bit line equalizer 140.
The memory cell 110 stores data and includes a cell transistor CT and a cell capacitor CC.
The bit line pre-sense amplifier 120 senses a potential difference between bit lines BL and BLB for a specific section in response to an active operation and amplifies the voltages of the bit lines BL and BLB based on the sensed potential difference. The bit line pre-sense amplifier 120 includes first and second NMOS transistors NM1 and NM2 connected to the bit lines BL and BLB, respectively, and third and fourth NMOS transistors NM3 and NM4 controlled in response to a gate control signal SG for a specific section when an active operation is performed. For reference, the bit line pre-sense amplifier 120 is often referred to as a low-Vt gated amplifier.
The bit line main sense amplifier 130 senses a potential difference between the bit lines BL and BLB and amplifies the voltages of the bit lines BL and BLB to a voltages of a pull-up driving power line RTO and a pull-down driving power line SB based on the sensed potential difference. The bit line main sense amplifier 130 includes first and second PMOS transistors PM1 and PM2 for driving the bit lines BL and BLB to the voltage of the pull-up driving power line RTO and fifth and sixth NMOS transistors NM5 and NM6 for driving the bit lines BL and BLB to the voltage of the pull-down driving power line SB.
The bit line equalizer 140 equalizes the voltages of the bit lines BL and BLB to a precharging voltage VBLP in a precharging operation section. The bit line equalizer 140 includes seventh to ninth NMOS transistors NM7, NM8, and NM9 controlled in response to a bit line equalization signal BLEQ. Here, the precharging voltage VBLP has a level half the core voltage VCORE, that is, a voltage level corresponding to data ‘1’.
The semiconductor memory device stores or outputs data by performing a write operation or a read operation after an active operation and then performs a precharging operation for a next active operation. The active operation and the precharging operation of the semiconductor memory device are described below.
First, when a word line WL is activated during an active operation, the cell transistor CT is turned on, and thus data stored in the cell capacitor CC is transferred to the primary bit line BL. Next, the bit line pre-sense amplifier 120 and the bit line main sense amplifier 130 amplify the primary bit line BL and the secondary bit line BLB to a core voltage VCORE, that is, the voltage of the pull-up driving power line RTO, and a ground voltage VSS, that is, the voltage of the pull-down driving power line SB by performing the respective sense amplification operation.
Next, when a precharging operation is performed, the bit line equalization signal BLEQ becomes a logic low level. In response, the seventh to ninth NMOS transistors NM7, NM8, and NM9 of the bit line equalizer 140 are turned on. Accordingly, the primary bit line BL and the secondary bit line BLB are driven to the precharging voltage VBLP, which is called the precharging operation of the bit lines BL and BLB.
The semiconductor memory device has the following concerns when an active operation and a precharging operation are performed.
First, during the active operation, the bit line pre-sense amplifier 120 and the bit line main sense amplifier 130 perform amplification operations using the ground voltage VSS as illustrated in the drawing and the above description. The ground voltage VSS is commonly vulnerable to noise and become even more vulnerable to noise when an amplification operation is performed. Accordingly, the bit line pre-sense amplifier 120 and the bit line main sense amplifier 130 that perform the amplification operations using the ground voltage VSS are very vulnerable to noise, which results in malfunction.
Next, when the precharging operation, the primary bit line BL and the secondary bit line BLB are precharged to the precharging voltage VBLP that has a level half the core voltage. In this state, if the gate control signal SG is affected by malfunction, the electrons of the bit lines BL and BLB precharged to the precharging voltage VBLP flow through the third and the fourth NMOS transistors NM3 and NM4. Next, the electrons flow into a terminal for the ground voltage VSS through the first and the second NMOS transistors NM1 and NM2. In other words, when the precharging operation is performed, an unnecessary current path may form in the first to fourth NMOS transistors NM1, NM2, NM3, and NM4, and current consumption through the leakage current path is unnecessarily generated.